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1 for more information www.analog.com document feedback all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 7705765, 7961132, 8319673, 9197235. typical application features description buffered octal, 16 - bit, 200ksps /ch differential 10.24v adc with 30v p-p common mode range the lt c ? 2358-16 is a 16-bit, low noise 8-channel simulta - neous sampling successive approximation register (sar) adc with buffered differential, wide common mode range picoamp inputs. operating from a 5v low voltage supply, flexible high voltage supplies, and using the internal refer - ence and buffer, each channel of this softspan tm adc can be independently configured on a conversion-by-conversion basis to accept 10.24v, 0v to 10.24v, 5.12v, or 0v to 5.12v signals. individual channels may also be disabled to increase throughput on the remaining channels. the integrated picoamp-input analog buffers, wide input common mode range and 128db cmrr of the lt c2358 -16 allow the adc to directly digitize a variety of signals us - ing minimal board space and power. this input signal flexibility, combined with 1lsb inl, no missing codes at 16 bits, and 94.2db snr, makes the lt c2358 -16 an ideal choice for many high voltage applications requiring wide dynamic range. the LTC2358-16 supports pin-selectable spi cmos (1.8v to 5v ) and lvds serial interfaces. between one and eight lanes of data output may be employed in cmos mode, allowing the user to optimize bus width and throughput. applications n 200ksps per channel throughput n eight buffered simultaneous sampling channels n 500pa/12na max input leakage at 85c/125c n 1lsb inl (maximum, 10.24v range) n guaranteed 16-bit, no missing codes n differential, wide common mode range inputs n per-channel softspan input ranges : 10.24v, 0v to 10.24v, 5.12v, 0v to 5.12v 12.5v, 0v to 12.5v, 6.25v, 0v to 6.25v n 94.2db single-conversion snr (typical) n ?111db thd (typical) at f in = 2khz n 128db cmrr (typical) at f in = 200hz n rail-to-rail input overdrive tolerance n integrated reference and buffer (4.096v) n spi cmos (1.8v to 5v) and lvds serial i/o n internal conversion clock, no cycle latency n 219mw power dissipation (27mw/ ch typical) n 48-lead (7mm x 7mm) lqfp package n programmable logic controllers n industrial process control n power line monitoring n test and measurement integral nonlinearity vs output code and channel a a r r a a a ra ra ra r ar arrar ar cs ? ? ? ? ? ? cmos ar a r ra r r lt c2358-16 rev a 32768 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 10.24v range inl error (lsb) 235816 ta01b true bipolar drive (in ? = 0v) all channels output code ?32768 ?16384 0 16384
2 for more information www.analog.com pin configuration absolute maximum ratings supply voltage (v cc ) ..................... C 0.3v to (v ee + 40v ) supply voltage (v ee ) ................................ C 17.4 v to 0.3v supply voltage difference (v cc C v ee ) ...................... 40v supply voltage (v dd ) .................................................. 6v supply voltage (ov dd ) ................................................ 6v internal regulated supply bypass (v ddlbyp ) ... (note 3) analog input voltage i n0 + to i n7 + , i n0 C to i n7 C (note 4) ......... (v ee C 0.3v ) to (v cc + 0.3v ) refin .................................................... C 0.3v to 2.8v refbuf, cnv (note 5) ............. C 0.3v to (v dd + 0.3v ) digital input voltage (note 5) ..... C 0.3v to (ov dd + 0.3v ) digital output voltage (note 5) .. C 0.3v to (ov dd + 0.3v ) power dissipation .............................................. 500mw operating temperature range lt c2358 c ................................................ 0 c to 70 c lt c2358 i ............................................. C 40 c to 85 c lt c2358 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) r r cmos cs aa a a t jmax = 150c, ja = 53c/w order information tray part marking* package description temperature range ltc2358clx-16#pbf ltc2358lx-16 48-lead (7mm 7mm) plastic lqfp 0c to 70c ltc2358ilx-16#pbf ltc2358lx-16 48-lead (7mm 7mm) plastic lqfp C40c to 85c ltc2358hlx-16#pbf ltc2358lx-16 48-lead (7mm 7mm) plastic lqfp C40c to 125c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http: //www.linear.com/leadfree/ http: //www.linear.com/product/LTC2358-16#orderinfo lt c2358-16 rev a
3 for more information www.analog.com electrical characteristics converter characteristics symbol parameter conditions min typ max units v in + absolute input range (in0 + to in7 + ) (note 7) l v ee + 4 v cc C 4 v v in C absolute input range (in0 C to in7 C ) (note 7) l v ee + 4 v cc C 4 v v in + C v in C input differential voltage range softspan 7: 2.5 ? v refbuf range (note 7) softspan 6: 2.5 ? v refbuf /1.024 range (note 7) softspan 5: 0v to 2.5 ? v refbuf range (note 7) softspan 4: 0v to 2.5 ? v refbuf /1.024 range (note 7) softspan 3: 1.25 ? v refbuf range (note 7) softspan 2: 1.25 ? v refbuf /1.024 range (note 7) softspan 1: 0v to 1.25 ? v refbuf range (note 7) l l l l l l l C 2.5 ? v refbuf C 2.5 ? v refbuf /1.024 0 0 C 1.25 ? v refbuf C 1.25 ? v refbuf /1.024 0 2.5 ? v refbuf 2.5 ? v refbuf /1.024 2.5 ? v refbuf 2.5 ? v refbuf /1.024 1.25 ? v refbuf 1.25 ? v refbuf /1.024 1.25 ? v refbuf v v v v v v v v cm input common mode voltage range (note 7) l v ee + 4 v cc C 4 v v in + C v in C input differential overdrive tolerance (note 8) l ?(v cc ? v ee ) (v cc ? v ee ) v i overdrive input overdrive current tolerance v in + > v cc , v in C > v cc (note 8) v in + < v ee , v in C < v ee (note 8) l l 0 10 ma ma i in analog input leakage current c-grade and i-grade h-grade l l 5 500 12 pa pa na r in analog input resistance for each pin >1000 g c in analog input capacitance 3 pf cmrr input common mode rejection ratio v in + = v in ? = 18v p-p 200hz sine l 100 128 db v ihcnv cnv high level input voltage l 1.3 v v ilcnv cnv low level input voltage l 0.5 v i incnv cnv input current v in = 0v to v dd l C10 10 a symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise softspans 7 and 6: 10.24v and 10v ranges softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges softspans 3 and 2: 5.12v and 5v ranges softspan 1: 0v to 5.12v range 0.35 0.7 0.5 1.1 lsb rms lsb rms lsb rms lsb rms inl integral linearity error softspans 7 and 6: 10.24v and 10v ranges (note 10) softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges (note 10) softspans 3 and 2: 5.12v and 5v ranges (note 10) softspan 1: 0v to 5.12v range (note 10) l l l l C1 C1.25 C1 C1.5 0.3 0.4 0.4 0.5 1 1.25 1 1.5 lsb lsb lsb lsb dnl differential linearity error (note 11) l C0.9 0.1 0.9 lsb zse zero-scale error (note 12) l C700 160 700 v zero-scale error drift 4 v/ c fse full-scale error v refbuf = 4.096v (refbuf overdriven) (note 12) l ?0.1 0.025 0.1 %fs full-scale error drift v refbuf = 4.096v (refbuf overdriven) (note 12) 2.5 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 6) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) lt c2358-16 rev a
4 for more information www.analog.com dynamic accuracy internal reference characteristics reference buffer characteristics symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l 91.5 86.7 88.8 83.5 94.1 89.6 91.6 86.5 db db db db snr signal-to-noise ratio softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l 91.7 86.8 88.9 83.6 94.2 89.7 91.6 86.5 db db db db thd total harmonic distortion softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l C111 C107 C113 C113 C101 C99 C101 C100 db db db db sfdr spurious free dynamic range softspans 7 and 6: 10.24v and 10v ranges, f in = 2khz softspans 5 and 4: 0v to 10.24v and 0v to 10v ranges, f in = 2khz softspans 3 and 2: 5.12v and 5v ranges, f in = 2khz softspan 1: 0v to 5.12v range, f in = 2khz l l l l 101 99 102 102 113 107 113 113 db db db db channel-to-channel crosstalk one channel converting 18v p-p 200hz sine in 10.24v range, crosstalk to all other channels ?109 db C3db input bandwidth 6 mhz aperture delay 1 ns aperture delay matching 150 ps aperture jitter 3 ps rms transient response full-scale step, 0.005% settling 420 ns symbol parameter conditions min typ max units v refin internal reference output voltage 2.043 2.048 2.053 v internal reference temperature coefficient (note 14) l 5 20 ppm/c internal reference line regulation v dd = 4.75v to 5.25v 0.1 mv/v internal reference output impedance 20 k v refin refin voltage range refin overdriven (note 7) 1.25 2.2 v symbol parameter conditions min typ max units v refbuf reference buffer output voltage refin overdriven, v refin = 2.048v l 4.091 4.096 4.101 v refbuf voltage range refbuf overdriven (notes 7, 15) l 2.5 5 v refbuf input impedance v refin = 0v, buffer disabled 13 k i refbuf refbuf load current v refbuf = 5v, 8 channels enabled (notes 15, 16) v refbuf = 5v, acquisition or nap mode (note 15) l 1.5 0.39 1.9 ma ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (notes 9, 13) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) lt c2358-16 rev a
5 for more information www.analog.com digital inputs and digital outputs symbol parameter conditions min typ max units cmos digital inputs and outputs v ih high level input voltage l 0.8???ov dd v v il low level input voltage l 0.2???ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i out = C500a l ov dd ? C ?0.2 v v ol low level output voltage i out = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C50 ma i sink output sink current v out = ov dd 50 ma lvds digital inputs and outputs v id differential input voltage l 200 350 600 mv r id on-chip input termination resistance cs = 0v, v icm = 1.2v cs = ov dd l 90 106 10 125 m v icm common-mode input voltage l 0.3 1.2 2.2 v i icm common-mode input current v in + = v in C = 0v to ov dd l C10 10 a v od differential output voltage r l = 100 differential termination l 275 350 425 mv v ocm common-mode output voltage r l = 100 differential termination l 1.1 1.2 1.3 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions min typ max units v cc supply voltage l 7.5 38 v v ee supply voltage l C16.5 0 v v cc ? v ee supply voltage difference l 10 38 v v dd supply voltage l 4.75 5.00 5.25 v i vcc supply current 200ksps sample rate, 8 channels enabled (note 17) acquisition mode (note 17) nap mode power down mode l l l l 4.6 8.5 2.9 6 5.3 9.8 3.3 15 ma ma ma a i vee supply current 200ksps sample rate, 8 channels enabled (note 17) acquisition mode (note 17) nap mode power down mode l l l l C5.5 C9.8 C3.5 C15 C4.5 C8 C2.8 C4 ma ma ma a cmos i/o mode ov dd supply voltage l 1.71 5.25 v i vdd supply current 200ksps sample rate, 8 channels enabled 200ksps sample rate, 8 channels enabled, v refbuf = 5v (note 15) acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l l 15.6 13.8 2.1 1.7 106 106 18 16 2.7 2.4 275 500 ma ma ma ma a a lt c2358-16 rev a
6 for more information www.analog.com symbol parameter conditions min typ max units i ovdd supply current 200ksps sample rate, 8 channels enabled (c l = 25pf) acquisition or nap mode power down mode l l l 1.7 1 1 2.6 20 20 ma a a p d power dissipation 200ksps sample rate, 8 channels enabled acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l 219 258 94 0.68 0.68 259 308 114 1.9 3 mw mw mw mw mw lvds i/o mode ov dd supply voltage l 2.375 5.25 v i vdd supply current 200ksps sample rate, 8 channels enabled 200ksps sample rate, 8 channels enabled, v refbuf = 5v (note 15) acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l l 18.4 16.8 3.7 3.4 106 106 20.7 19.2 4.5 4.1 275 500 ma ma ma ma a a i ovdd supply current 200ksps sample rate, 8 channels enabled (r l = 100) acquisition or nap mode (r l = 100) power down mode l l l 7 7 1 8.5 8.0 20 ma ma a p d power dissipation 200ksps sample rate, 8 channels enabled acquisition mode nap mode power down mode (c-grade and i-grade) power down mode (h-grade) l l l l l 245 284 120 0.68 0.68 287 337 143 1.9 3 mw mw mw mw mw symbol parameter conditions min typ max units f smpl maximum sampling frequency 8 channels enabled 7 channels enabled 6 channels enabled 5 channels enabled 4 channels enabled 3 channels enabled 2 channels enabled 1 channel enabled l l l l l l l l 200 225 250 300 350 425 550 800 ksps ksps ksps ksps ksps ksps ksps ksps t cyc time between conversions 8 channels enabled, f smpl = 200ksps 7 channels enabled, f smpl = 225ksps 6 channels enabled, f smpl = 250ksps 5 channels enabled, f smpl = 300ksps 4 channels enabled, f smpl = 350ksps 3 channels enabled, f smpl = 425ksps 2 channels enabled, f smpl = 550ksps 1 channel enabled, f smpl = 800ksps l l l l l l l l 5000 4444 4000 3333 2855 2350 1815 1250 ns ns ns ns ns ns ns ns t conv conversion time n channels enabled, 1 n 8 l 450?n 500?n 550?n ns t acq acquisition time (t acq = t cyc C t conv C t busylh ) 8 channels enabled, f smpl = 200ksps 7 channels enabled, f smpl = 225ksps 6 channels enabled, f smpl = 250ksps 5 channels enabled, f smpl = 300ksps 4 channels enabled, f smpl = 350ksps 3 channels enabled, f smpl = 425ksps 2 channels enabled, f smpl = 550ksps 1 channel enabled, f smpl = 800ksps l l l l l l l l 570 564 670 553 625 670 685 670 980 924 980 813 835 830 795 730 ns ns ns ns ns ns ns ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) power requirements adc timing characteristics lt c2358-16 rev a
7 for more information www.analog.com the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) adc timing characteristics symbol parameter conditions min typ max units t cnvh cnv high time l 40 ns t cnvl cnv low time l 750 ns t busylh cnv? to busy delay c l = 25pf l 30 ns t quiet digital i/o quiet time from cnv ? l 20 ns t pdh pd high time l 40 ns t pdl pd low time l 40 ns t wake refbuf wake-up time c refbuf = 47f, c refin = 0.1f 200 ms cmos i/o mode t scki scki period (notes 18, 19) l 10 ns t sckih scki high time l 4 ns t sckil scki low time l 4 ns t ssdiscki sdi setup time from scki ? (note 18) l 2 ns t hsdiscki sdi hold time from scki ? (note 18) l 1 ns t dsdoscki sdo data valid delay from scki ? c l = 25pf (note 18) l 7.5 ns t hsdoscki sdo remains valid delay from scki ? c l = 25pf (note 18) l 1.5 ns t skew sdo to scko skew (note 18) l C1 0 1 ns t dsdobusyl sdo data valid delay from busy ? c l = 25pf (note 18) l 0 ns t en bus enable time after cs? (note 18) l 15 ns t dis bus relinquish time after cs? (note 18) l 15 ns lvds i/o mode t scki scki period (note 20) l 4 ns t sckih scki high time (note 20) l 1.5 ns t sckil scki low time (note 20) l 1.5 ns t ssdiscki sdi setup time from scki (notes 11, 20) l 1.2 ns t hsdiscki sdi hold time from scki (notes 11, 20) l C0.2 ns t dsdoscki sdo data valid delay from scki (notes 11, 20) l 6 ns t hsdoscki sdo remains valid delay from scki (notes 11, 20) l 1 ns t skew sdo to scko skew (note 11) l C0.4 0 0.4 ns t dsdobusyl sdo data valid delay from busy ? (note 11) l 0 ns t en bus enable time after cs? l 50 ns t dis bus relinquish time after cs? l 15 ns lt c2358-16 rev a
8 for more information www.analog.com cmos timings 0.8 ? ov dd 0.2 ? ov dd 50% 50% 235816 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay lvds timings (differential) +200mv ?200mv 0v 0v 235816 f01b ?200mv +200mv ?200mv +200mv t delay t width t delay figure 1. voltage levels for timing specifications note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: v ddlbyp is the output of an internal voltage regulator, and should only be connected to a 2.2f ceramic capacitor to bypass the pin to gnd, as described in the pin functions section. do not connect this pin to any external circuitry. note 4: when these pin voltages are taken below v ee or above v cc , they will be clamped by internal diodes. this product can handle input currents of up to 100ma below v ee or above v cc without latchup. note 5: when these pin voltages are taken below gnd or above v dd or ov dd , they will be clamped by internal diodes. this product can handle currents of up to 100ma below ground or above v dd or ov dd without latchup. note 6: C16.5v v ee 0v, 7.5v v cc 38v, 10v (v cc C v ee ) 38v, v dd? =?5v , unless otherwise specified. note 7: recommended operating conditions. note 8: exceeding these limits on any channel may corrupt conversion results on other channels. driving an analog input above v cc on any channel up to 10ma will not affect conversion results on other channels. driving an analog input below v ee may corrupt conversion results on other channels. refer to applications information section for further details. refer to absolute maximum ratings section for pin voltage limits related to device reliability. note 9: v cc = 15v, v ee = C15v, v dd = 5v, ov dd? =?2.5v, f smpl = 200ksps, internal reference and buffer, true bipolar input signal drive in bipolar softspan ranges, unipolar signal drive in unipolar softspan ranges, unless otherwise specified. note 10: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 11: guaranteed by design, not subject to test. note 12: for bipolar softspan ranges 7, 6, 3, and 2, zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. full-scale error for these softspan ranges is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. for unipolar softspan ranges 5, 4, and 1, zero-scale error is the offset voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001. full-scale error for these softspan ranges is the worst-case deviation of the last code transition from ideal and includes the effect of offset error. note 13: all specifications in db are referred to a full-scale input in the relevant softspan input range, except for crosstalk, which is referred to the crosstalk injection signal amplitude. note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 15: when refbuf is overdriven, the internal reference buffer must be disabled by setting refin = 0v. note 16: i refbuf varies proportionally with sample rate and the number of active channels. note 17: analog input buffer supply currents from i vcc and i vee are reduced outside the acquisition period. refer to nap mode in applications information section. note 18: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v, and ov dd = 5.25v. note 19: a t scki period of 10ns minimum allows a shift clock frequency of up to 100mhz for rising edge capture. note 20: v icm = 1.2v, v id = 350mv for lvds differential input pairs. adc timing characteristics lt c2358-16 rev a
9 for more information www.analog.com typical performance characteristics integral nonlinearity vs output code and range integral nonlinearity vs output code and range integral nonlinearity vs output code and range integral nonlinearity vs output code dc histogram (zero-scale) dc histogram (near full-scale) integral nonlinearity vs output code and channel integral nonlinearity vs output code and channel differential nonlinearity vs output code and channel t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps , unless otherwise noted. lt c2358-16 rev a 32768 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 inl error (lsb) 235816 g05 unipolar drive (in ? = 0v) ?1.00 one channel 0v to 5.12v range 0v to 10.24v and 0v to 10v ranges output code 0 16384 32768 49152 65536 ?0.75 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 inl error (lsb) ?0.50 235816 g06 10.24v range true bipolar drive (in ? = 0v) arbitrary drive in + /in ? common mode swept ?10.24v to 10.24v output code ?32768 ?16384 0 ?0.25 16384 32768 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 0 1.00 inl error (lsb) 235816 g07 10.24v range code ?4 ?3 ?2 ?1 0 0.25 1 2 3 4 0 20000 40000 60000 80000 100000 0.50 120000 140000 160000 180000 counts 235816 g08 10.24v range code 32759 32761 0.75 32763 32765 32767 0 20000 40000 60000 80000 100000 120000 1.00 140000 160000 180000 counts 235816 g09 10.24v range inl error (lsb) 235816 g01 10.24v range fully differential drive (in ? = ?in + ) all channels output code ?32768 ?16384 0 16384 true bipolar drive (in ? = 0v) 32768 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 all channels inl error (lsb) 235816 g02 all ranges all channels output code 0 16384 32768 49152 65536 output code ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.0 0.1 0.2 0.3 0.4 ?32768 0.5 dnl error (lsb) 235816 g03 true bipolar drive (in ? = 0v) one channel 10.24v and 10v ranges 5.12v and 5v ranges output code ?16384 ?32768 ?16384 0 16384 32768 ?1.00 ?0.75 ?0.50 ?0.25 0 0 0.25 0.50 0.75 1.00 inl error (lsb) 235816 g04 fully differential drive (in ? = ?in + ) one channel 10.24v and 10v ranges 16384 5.12v and 5v ranges output code ?32768 ?16384 0 16384 32768 ?1.00 ?0.75
10 for more information www.analog.com typical performance characteristics 32k point fft f smpl = 200khz, f in ?=?2khz snr, sinad vs v refbuf , f in ?=?2khz thd, harmonics vs v refbuf , f in ?=?2khz snr, sinad vs input frequency thd vs input frequency thd, harmonics vs input common mode, f in = 2khz 32k point fft f smpl ?=?200khz, f in ?=?2khz 32k point fft f smpl ?=?200khz, f in ?=?2khz 32k point arbitrary two-tone fft f smpl ?=?200khz, in + ?=?C 7dbfs 2khz sine, in C ?=?C 7dbfs 3.1khz sine t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps , unless otherwise noted. lt c2358-16 rev a 20 235816 g13 snr sinad 2.5 ? v refbuf range true bipolar drive (in C = 0v) refbuf voltage (v) 2.5 3 3.5 4 40 4.5 5 91 92 93 94 95 96 snr, sinad (dbfs) 235816 g14 60 thd 2nd 3rd 2.5 ? v refbuf range true bipolar drive (in C = 0v) refbuf voltage (v) 2.5 3 3.5 4 80 4.5 5 C135 C130 C125 C120 C115 C110 C105 thd, harmonics (dbfs) 100 235816 g15 snr sinad 10.24v range true bipolar drive (in C = 0v) frequency (hz) 10 100 1k 10k ?180 100k 60 65 70 75 80 85 90 95 100 ?160 snr, sinad (dbfs) 235816 g16 10.24v range true bipolar drive (in ? = 0v) 50 source 1k source 10k ?140 source frequency (hz) 10 100 1k 10k 100k ?130 ?120 ?110 ?120 ?100 ?90 ?80 ?70 ?60 thd, harmonics (dbfs) 235816 g17 2nd thd 3rd ?100 2v p?p fully differential drive ?11v v cm 11v 10.24v range input common mode (v) ?15 ?10 ?5 0 5 10.24v range ?80 10 15 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 ?60 0 thd, harmonics (dbfs) 235816 g18 ?40 ?20 0 amplitude (dbfs) 235816 g10 10.24v range fully differential drive (in ? = ?in + ) snr = 94.3db true bipolar drive (in ? = 0v) thd = ?115db sinad = 94.3db sfdr = 120db frequency (khz) 0 20 40 60 80 100 snr = 94.3db ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 thd = ?111db amplitude (dbfs) 235816 g11 10.24v range arbitrary drive sfdr = 118db snr = 94.3db 6.2khz frequency (khz) 0 20 sinad = 94.2db 40 60 80 100 ?180 ?160 ?140 ?120 ?100 ?80 sfdr = 113db ?60 ?40 ?20 0 amplitude (dbfs) 235816 g12 5.12v range true bipolar drive (in ? = 0v) snr = 91.8db thd = ?113db frequency (khz) sinad = 91.7db sfdr = 116db frequency (khz) 0 20 40 60 80 100 ?180 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs)
11 for more information www.analog.com typical performance characteristics snr, sinad vs temperature, f in ?=?2khz thd, harmonics vs temperature, f in = 2khz inl, dnl vs temperature analog input leakage current vs temperature positive full-scale error vs temperature and channel zero-scale error vs temperature and channel snr, sinad vs input level, f in ?=?2khz cmrr vs input frequency and channel crosstalk vs input frequency and channel t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps , unless otherwise noted. lt c2358-16 rev a 100k temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 1m 125 ?125 ?120 ?115 ?110 ?105 ?100 ?95 thd, harmonics (dbfs) 235816 g23 60 max inl min inl max dnl min dnl 10.24v range true bipolar drive (in ? = 0v) all channels temperature (c) ?55 ?35 70 ?15 5 25 45 65 85 105 125 ?1.00 ?0.75 80 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 inl, dnl error (lsb) 235816 g24 10.24v range 90 refbuf overdriven v refbuf = 4.096v all channels temperature (c) ?55 ?35 ?15 5 25 45 100 65 85 105 125 ?0.100 ?0.075 ?0.050 ?0.025 0.000 0.025 110 0.050 0.075 0.100 full-scale error (%) 235816 g26 10.24v range all channels temperature (c) ?55 ?35 120 ?15 5 25 45 65 85 105 125 ?3 ?2 130 ?1 0 1 2 3 zero-scale error (lsb) 235816 g27 16 analog input pin traces for each input voltage in = 0v 10.24v range 140 in = +10v in = ?10v temperature (c) ?55 ?35 ?15 5 25 45 65 cmrr (db) 85 105 125 0.1 1 10 100 1k 10k analog input leakage current (pa) 235816 g20 235816 g25 ch1 10.24v range in0 + = 0v in0 ? = 18v p?p sine all channels converting ch7 ch2 in + = in ? = 18v p?p sine frequency (hz) 10 100 1k 10k 100k 1m ?135 ?130 ?125 all channels ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 crosstalk (db) frequency (hz) 235816 g21 snr sinad 10.24v range true bipolar drive (in ? = 0v) input level (dbfs) ?40 ?30 ?20 ?10 10 0 94.0 94.2 94.4 94.6 94.8 95.0 snr, sinad (dbfs) 235816 g19 snr 100 sinad 10.24v range true bipolar drive (in ? = 0v) temperature (c) ?55 ?35 ?15 5 25 45 1k 65 85 105 125 92.0 92.5 93.0 93.5 94.0 94.5 10k 95.0 95.5 96.0 snr, sinad (dbfs) 235816 g22 thd 2nd 3rd 10.24v range true bipolar drive (in ? = 0v)
12 for more information www.analog.com typical performance characteristics supply current vs sampling rate power dissipation vs sampling rate, n-channels enabled step response (large-signal settling) supply current vs temperature power-down current vs temperature offset error vs input common mode internal reference output vs temperature t a = 25c, v cc ?=?+15v, v ee ?=?C15v, v dd ?=?5v, ov dd ?=?2.5v, internal reference and buffer (v refbuf ?=?4.096v), f smpl = 200ksps , unless otherwise noted. psrr vs frequency step response (fine settling) lt c2358-16 rev a 5 16 supply current (ma) 235816 g33 v cc ov dd v ee v dd in + = in ? = 0v frequency (hz) 10 25 100 1k 10k 100k 50 60 70 80 90 100 45 110 120 130 140 150 psrr (db) 235816 g30 v cc = 38v, v ee = 0v v cm = 4v to 34v 10.24v range 65 v cc = 21.5v, v ee = ?16.5v v cm = ?12.5v to 17.5v input common mode (v) ?17 0 17 34 ?2.0 ?1.5 ?1.0 85 ?0.5 0 0.5 1.0 1.5 2.0 offset error (lsb) 235816 g31 10.24v range in + = 199.99987khz square wave 105 in ? = 0v settling time (ns) ?100 0 100 200 300 400 500 600 125 700 800 900 ?32768 ?24576 ?16384 ?8192 0 8192 16384 ?6 24576 32768 output code (lsb) 235816 g35 10.24v range in + = 199.99987khz square wave in ? = 0v settling time (ns) ?100 ?4 0 100 200 300 400 500 600 700 800 900 ?2 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 i ovdd 0 100 deviation from final value (lsb) 235816 g36 with nap mode t cnvl = 750ns n = 8 n = 1 n = 2 n = 4 sampling frequency (khz) 2 0 100 200 300 400 500 600 700 800 80 4 100 120 140 160 180 200 220 240 260 power dissipation (mw) 6 235816 g34 8 10 12 14 16 18 i vdd supply current (ma) 235816 g28 i ovdd i vdd ?i vee i vcc temperature (c) ?55 ?35 ?15 i vee 5 25 45 65 85 105 125 0.01 0.1 1 i vcc 10 100 1000 power-down current (a) 235816 g29 15 units temperature (c) ?55 ?35 ?15 temperature (c) 5 25 45 65 85 105 125 2.045 2.046 2.047 ?55 2.048 2.049 2.050 2.051 internal reference output (v) 235816 g32 i ovdd i vdd i vee i vcc ?35 with nap mode t cnvl = 1s sampling frequency (khz) 0 40 80 120 160 200 ?6 ?15 ?4 ?2 0 2 4 6 8 10 12 14
13 for more information www.analog.com pin functions pins that are the same for all digital i/o modes i n0 + /in0 C to in7 + /in7 C (pins 14/13, 12/11, 10/9, 8/7, 6/5, 4/3, 2/1, and 48/47): positive and negative analog inputs, channels 0 to 7. the converter simultaneously samples and digitizes (v in + C v in C) for all channels. wide input common mode range (v ee + 4v? v cm v cc C 4v) and high common mode rejection allow the inputs to accept a wide variety of signal swings. full-scale input range is determined by the channels softspan configuration. gnd (pins 15, 18, 20, 30, 41, 44, 46): ground. solder all gnd pins to a solid ground plane. v cc (pin 16) : positive high voltage power supply. the range of v cc is 7.5v to 38v with respect to gnd and 10v to 38v with respect to v ee . bypass v cc to gnd close to the pin with a 0.1f ceramic capacitor. v ee (pins 17, 45): negative high voltage power supply. the range of v ee is 0v to C16.5v with respect to gnd and C10v to C38v with respect to v cc . connect pins 17 and 45 together and bypass the v ee network to gnd close to pin 17 with a 0.1f ceramic capacitor. in applications where v ee is shorted to gnd, this capacitor may be omitted. refin (pin 19): bandgap reference output/reference buf - fer input. an internal bandgap reference nominally outputs 2.048v on this pin. an internal reference buffer amplifies v refin to create the converter master reference voltage v refbuf = 2? ??v refin on the refbuf pin. when using the internal reference, bypass refin to gnd (pin 20) close to the pin with a 0.1f ceramic capacitor to filter the bandgap output noise. if more accuracy is desired, overdrive refin with an external reference in the range of 1.25v to 2.2v. do not load this pin when internal reference is used. refbuf (pin 21): internal reference buffer output. an internal reference buffer amplifies v refin to create the converter master reference voltage v refbuf = 2? ? ?v refin on this pin, nominally 4.096v when using the internal bandgap reference. bypass refbuf to gnd (pin 20) close to the pin with a 47f ceramic capacitor. the internal ref - erence buffer may be disabled by grounding its input at refin. with the buffer disabled, overdrive refbuf with an external reference voltage in the range of 2.5v to 5v. when using the internal reference buffer, limit the loading of any external circuitry connected to refbuf to less than 200a. using a high input impedance amplifier to buffer v refbuf to any external circuits is recommended. pd (pin 22): power down input. when this pin is brought high, the LTC2358-16 is powered down and subsequent conversion requests are ignored. if this occurs during a conversion, the device powers down once the conversion completes. if this pin is brought high twice without an intervening conversion, an internal global reset is initi - ated, equivalent to a power-on-reset event. logic levels are determined by ov dd . lvds/ cmos (pin 23): i/o mode select. tie this pin to ov dd to select lvds i/o mode, or to ground to select cmos i/o mode. logic levels are determined by ov dd . cnv (pin 24): conversion start input. a rising edge on this pin puts the internal sample-and-holds into the hold mode and initiates a new conversion. cnv is not gated by cs, allowing conversions to be initiated independent of the state of the serial i/o bus. busy (pin 38): busy output. the busy signal indicates that a conversion is in progress. this pin transitions low- to-high at the start of each conversion and stays high until the conversion is complete. logic levels are determined by ov dd . v ddlbyp (pin 40): internal 2.5v regulator bypass pin. the voltage on this pin is generated via an internal regulator operating off of v dd . this pin must be bypassed to gnd close to the pin with a 2.2f ceramic capacitor. do not connect this pin to any external circuitry. v dd (pins 42, 43): 5v power supply. the range of v dd is 4.75v to 5.25v. connect pins 42 and 43 together and bypass the v dd network to gnd with a shared 0.1f ceramic capacitor close to the pins. lt c2358-16 rev a
14 for more information www.analog.com pin functions cmos i/o mode sdo0 to sdo7 (pins 25, 26, 27, 28, 33, 34, 35, and 36): cmos serial data outputs, channels 0 to 7. the most recent conversion result along with channel configuration information is clocked out onto the sdo pins on each ris - ing edge of scki. output data formatting is described in the digital interface section. leave unused sdo outputs unconnected. logic levels are determined by ov dd . scki (pin 29) : cmos serial clock input. drive scki with the serial i/o clock. scki rising edges latch serial data in on sdi and clock serial data out on sdo0 to sdo7. for standard spi bus operation, capture output data at the receiver on rising edges of scki. scki is allowed to idle either high or low. logic levels are determined by ov dd . ov dd (pin 31): i/o interface power supply. in cmos i/o mode, the range of ov dd is 1.71v to 5.25v . bypass ov dd to gnd (pin 30) close to the pin with a 0.1f ceramic capacitor. scko (pin 32): cmos serial clock output. scki rising edges trigger transitions on scko that are skew-matched to the serial output data streams on sdo0 to sdo7. the resulting scko frequency is half that of scki. rising and falling edges of scko may be used to capture sdo data at the receiver (fpga) in double data rate (ddr) fashion. for standard spi bus operation, scko is not used and should be left unconnected. scko is forced low at the falling edge of busy. logic levels are determined by ov dd . sdi (pin 37): cmos serial data input. drive this pin with the desired 24- bit softspan configuration word (see table 1a ), latched on the rising edges of scki. if all channels will be configured to operate only in softspan 7, tie sdi to ov dd . logic levels are determined by ov dd . cs (pin 39): chip select input. the serial data i/o bus is enabled when cs is low and is disabled and hi-z when cs is high. cs also gates the external shift clock, scki. logic levels are determined by ov dd . lvds i/o mode sdo0, sdo7, sdi (pins 25, 36, and 37): cmos serial data i/o. in lvds i/o mode, these pins are hi-z. sdi + /sdi C (pins 26/27): lvds positive and negative serial data input. differentially drive sdi + /sdi C with the desired 24- bit softspan configuration word (see table 1a), latched on both the rising and falling edges of scki + /scki C . the sdi + /sdi C input pair is internally terminated with a 100 differential resistor when cs is low. scki + /scki C (pins 28/29): lvds positive and negative serial clock input. differentially drive scki + /scki C with the serial i/o clock. scki + /scki C rising and falling edges latch serial data in on sdi + /sdi C and clock serial data out on sdo + /sdo C . idle scki + /scki C low, including when transitioning cs. the scki + /scki C input pair is internally terminated with a 100 differential resistor when cs is low. ov dd (pin 31) : i/o interface power supply. in lvds i/o mode, the range of ov dd is 2.375v to 5.25v . bypass ov dd to gnd (pin 30) close to the pin with a 0.1f ceramic capacitor. scko + /scko C (pins 32/33): lvds positive and negative serial clock output. scko + /scko C outputs a copy of the input serial i/o clock received on scki + /scki C , skew- matched with the serial output data stream on sdo + /sdo C . use the rising and falling edges of scko + /scko C to cap - ture sdo + /sdo C data at the receiver (fpga). the scko + / scko C output pair must be differentially terminated with a 100 resistor at the receiver (fpga). sdo + /sdo C (pins 34/35): lvds positive and negative serial data output. the most recent conversion result along with channel configuration information is clocked out onto sdo + /sdo C on both rising and falling edges of scki + /scki C , beginning with channel 0. the sdo + /sdo C output pair must be differentially terminated with a 100 resistor at the receiver (fpga). cs (pin 39): chip select input. the serial data i/o bus is enabled when cs is low, and is disabled and hi-z when cs is high. cs also gates the external shift clock, scki + / scki C . the internal 100 differential termination resistors on the scki + /scki C and sdi + /sdi C input pairs are disabled when cs is high. logic levels are determined by ov dd . lt c2358-16 rev a
15 for more information www.analog.com configuration tables table 1a. softspan configuration table. use this table with table 1b to choose independent binary softspan codes ss[2:0] for each channel based on desired analog input range. combine softspan codes to form 24- bit softspan configuration word s[23:0]. use serial interface to write softspan configuration word to LTC2358-16, as shown in figure 18 binary softspan code ss[2:0] analog input range full scale range binary format of conversion result 111 2.5 ? v refbuf 5 ? v refbuf tw o s complement 110 2.5 ? v refbuf /1.024 5 ? v refbuf /1.024 tw o s complement 101 0v to 2.5 ? v refbuf 2.5 ? v refbuf straight binary 100 0v to 2.5 ? v refbuf /1.024 2.5 ? v refbuf /1.024 straight binary 011 1.25 ? v refbuf 2.5 ? v refbuf tw o s complement 010 1.25 ? v refbuf /1.024 2.5 ? v refbuf /1.024 tw o s complement 001 0v to 1.25 ? v refbuf 1.25 ? v refbuf straight binary 000 channel disabled channel disabled all zeros table 1b. reference configuration table. the LTC2358-16 supports three reference configurations. analog input range scales with the converter master reference voltage, v refbuf reference configuration v refin v refbuf binary softspan code ss[2:0] analog input range internal reference with internal buffer 2.048v 4.096v 111 10.24v 110 10v 101 0v to 10.24v 100 0v to 10v 011 5.12v 010 5v 001 0v to 5.12v external reference with internal buffer (refin pin externally overdriven) 1.25v (min value) 2.5v 111 6.25v 110 6.104v 101 0v to 6.25v 100 0v to 6.104v 011 3.125v 010 3.052v 001 0v to 3.125v 2.2v (max value) 4.4v 111 11v 110 10.742v 101 0v to 11v 100 0v to 10.742v 011 5.5v 010 5.371v 001 0v to 5.5v lt c2358-16 rev a
16 for more information www.analog.com reference configuration v refin v refbuf binary softspan code ss[2:0] analog input range external reference unbuffered (refbuf pin externally overdriven, refin pin grounded) 0v 2.5v (min value) 111 6.25v 110 6.104v 101 0v to 6.25v 100 0v to 6.104v 011 3.125v 010 3.052v 001 0v to 3.125v 0v 5v (max value) 111 12.5v 110 12.207v 101 0v to 12.5v 100 0v to 12.207v 011 6.25v 010 6.104v 001 0v to 6.25v configuration tables table 1b. reference configuration table (continued). the LTC2358-16 supports three reference configurations. analog input range scales with the converter master reference voltage, v refbuf lt c2358-16 rev a
17 for more information www.analog.com functional block diagram sdo0 sdo7 scko sdi scki cs in0 + in0 ? busy 16-bit sar adc cmos serial i/o interface 235816 bd01 16 bits reference buffer refbuf refin gnd v cc v ee v ddlbyp v dd ov dd LTC2358-16 control logic 2.048v reference 2.5v regulator lvds/ cmos pd cnv in1 + in1 ? s/h s/h s/h s/h s/h s/h s/h s/h in2 + in2 ? in3 + in3 ? in4 + in4 ? in5 + in5 ? in6 + in6 ? in7 + in7 ? 8-channel multiplexer 20k 2 ? ? ? buffers sdo + sdo ? scko + scko ? sdi + sdi ? scki + scki ? cs in0 + in0 ? busy 16-bit sar adc lvds serial i/o interface 235816 bd02 16 bits reference buffer refbuf refin gnd v cc v ee v ddlbyp v dd ov dd LTC2358-16 control logic 2.048v reference 2.5v regulator lvds/ cmos pd cnv s/h in1 + in1 ? s/h in2 + in2 ? s/h in3 + in3 ? s/h in4 + in4 ? s/h in5 + in5 ? s/h in6 + in6 ? s/h in7 + in7 ? s/h 8-channel multiplexer 20k 2 buffers lvds i/o mode cmos i/o mode lt c2358-16 rev a
18 for more information www.analog.com timing diagram lvds i/o mode cmos i/o mode s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3 s4 s1 s2 s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 ss1 ss2 ss0 d15 d14 d13 cnv (cmos) cs = pd = 0 235816 td02 convert don?t care acquire busy (cmos) scko (lvds) sdo (lvds) scki (lvds) sdi (lvds) don?t care sample n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sample n + 1 softspan configuration word for conversion n + 1 channel 0 conversion n channel 1 conversion n channel 7 conversion n conversion result channel id softspan 186 187 188 189 190 191 192 0 ss1 ss2 ss0 d15 channel 0 conversion n conversion result channel id softspan c2 c1 c0 c2 c1 c0 s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3 s4 s1 s2 s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 c2 c1 c0 c2 c1 c0 ss1 ss2 ss0 d15 cnv cs = pd = 0 convert don?t care acquire busy sdo7 scko sdo0 scki sdi don?t care sample n sample n + 1 softspan configuration word for conversion n + 1 channel 0 conversion n channel 1 conversion n channel 7 conversion n channel 0 conversion n 235816 td01 conversion result channel id softspan conversion result d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 ss1 ss2 ss0 d15 don?t care conversion result channel id softspan conversion result ? ? ? lt c2358-16 rev a
19 for more information www.analog.com applications information overview the LTC2358-16 is a 16-bit, low noise 8-channel simul - taneous sampling successive approximation register (sar) adc with buffered differential, wide common mode range picoamp inputs. the adc operates from a 5v low voltage supply and flexible high voltage supplies, nominally 15v. using the integrated low-drift reference and buffer (v refbuf = 4.096v nominal), each channel of this softspan adc can be independently configured on a conversion-by-conversion basis to accept 10.24v, 0v to 10.24v, 5.12v , or 0v to 5.12v signals. the input signal range may be expanded up to 12.5v using an external 5v reference. individual channels may also be disabled to increase throughput on the remaining channels. the integrated picoamp-input analog buffers, wide input common mode range, and 128db cmrr of the ltc2358- 16 allow the adc to directly digitize a variety of signals using minimal board space and power. this input signal flexibility, combined with 1lsb inl, no missing codes at 16 bits, and 94.2db snr, makes the LTC2358-16 an ideal choice for many high voltage applications requiring wide dynamic range. the absolute common mode input range (v ee ? +? 4v to v cc ? C? 4v) is determined by the choice of high voltage supplies. these supplies may be biased asymmetrically around ground and include the ability for v ee to be tied directly to ground. the LTC2358-16 supports pin-selectable spi cmos (1.8v to 5v ) and lvds serial interfaces, enabling it to com - municate equally well with legacy microcontrollers and modern fpgas. in cmos mode, applications may employ between one and eight lanes of serial output data, allowing the user to optimize bus width and data throughput. the ltc2358 -16 typically dissipates 219mw when converting eight channels simultaneously at 200ksps per channel. optional nap and power down modes may be employed to further reduce power consumption during inactive periods. converter operation the LTC2358-16 operates in two phases. during the ac - quisition phase, the sampling capacitors in each channel s sample-and-hold (s/h) circuit connect to their respective analog input buffers, which track the differential analog input voltage (v in + C v in C ). a rising edge on the cnv pin transitions all channels s/h circuits from track mode to hold mode, simultaneously sampling the input signals on all channels and initiating a conversion. during the conversion phase, each channel s sampling capacitors are connected, one channel at a time, to a 16- bit charge redistribution capacitor d/a converter (cdac). the cdac is sequenced through a successive approximation algo - rithm, effectively comparing the sampled input voltage with binary-weighted fractions of the channel s softspan full-scale range (e.g., v fsr /2, v fsr /4 v fsr /65536) us - ing a differential comparator. at the end of this process, the cdac output approximates the channels sampled analog input. once all channels have been converted in this manner, the adc control logic prepares the 16-bit digital output codes from each channel for serial transfer. transfer function the ltc2358 -16 digitizes each channel s full-scale voltage range into 2 16 levels. in conjunction with the adc master reference voltage, v refbuf , a channels softspan configu - ration determines its input voltage range, full-scale range, lsb size, and the binary format of its conversion result, as shown in tables 1a and 1b. for example, employing the internal reference and buffer (v refbuf = 4.096v nominal), softspan 7 configures a channel to accept a 10.24v bi - polar analog input voltage range, which corresponds to a 20.48v full-scale range with a 312.5v lsb. other softspan configurations and reference voltages may be employed to convert both larger and smaller bipolar and unipolar input ranges. conversion results are output in twos comple - ment binary format for all bipolar softspan ranges, and in straight binary format for all unipolar softspan ranges. lt c2358-16 rev a
20 for more information www.analog.com the ideal two s complement transfer function is shown in figure 2, while the ideal straight binary transfer function is shown in figure 3. input voltage (v) 0v output code (two?s complement) ?1 lsb 235816 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/65536 figure 2. ltc2358 -16 two s complement transfer function input voltage (v) output code (straight binary) 235816 f03 111...111 111...110 100...001 100...000 000...000 000...001 011...110 unipolar zero 011...111 fsr ? 1lsb 0v fsr = +fs 1lsb = fsr/65536 figure 3. ltc2358 -16 straight binary transfer function buffered analog inputs each channel of the LTC2358-16 simultaneously samples the voltage difference (v in +? C?v in C) between its analog input pins over a wide common mode input range while attenuating unwanted signals common to both input pins by the common-mode rejection ratio (cmrr) of the adc. wide common mode input range coupled with high cmrr allows the in + /in C analog inputs to swing with an arbitrary relationship to each other, provided each pin remains between (v ee ?+? 4v) and (v cc ? C? 4v). this feature of the applications information LTC2358-16 enables it to accept a wide variety of signal swings, including traditional classes of analog input signals such as pseudo-differential unipolar, pseudo-differential true bipolar, and fully differential, simplifying signal chain design. for conversion of signals extending to v ee , the unbuffered ltc2348-16 adc is recommended. the wide operating range of the high voltage supplies offers further input common mode flexibility. as long as the voltage difference limits of 10v? ?(v cc ? C?v ee )? ? 38v are observed, v cc and v ee may be independently biased anywhere within their own individually allowed operating ranges, including the ability for v ee to be tied directly to ground. this feature enables the common mode input range of the LTC2358-16 to be tailored to specific ap - plication requirements. in all softspan ranges, each channels analog inputs can be modeled by the equivalent circuit shown in figure 4. at the start of acquisition, the sampling capacitors (c samp ) connect to the integrated buffers buffer + /buffer C through the sampling switches. the sampled voltage is reset dur - ing the conversion process and is therefore re-acquired for each new conversion. the diodes between the inputs and the v cc and v ee sup - plies provide input esd protection. while within the supply voltages, the analog inputs of the LTC2358-16 draw only 5pa typical dc leakage current and the esd protection diodes don t turn on. this offers a significant advantage over external op amp buffers, which often have diode protection that turns on during transients and corrupts the voltage on any filter capacitors at their inputs. in + r samp 750 r samp 750 c samp 30pf c samp 30pf v cc v cc v ee v ee bias voltage in ? 235816 f04 buffer + buffer ? figure 4. equivalent circuit for differential analog inputs, single channel shown lt c2358-16 rev a
21 for more information www.analog.com applications information bipolar softspan input ranges for channels configured in softspan ranges 7, 6, 3, or 2, the LTC2358-16 digitizes the differential analog input voltage (v in + C v in C ) over a bipolar span of 2.5? ??v refbuf , 2.5? ??v refbuf /1.024, 1.25? ??v refbuf , or 1.25? ??v refbuf /1.024, respectively, as shown in table 1a. these softspan ranges are useful for digitizing input signals where in + and in C swing above and below each other. traditional examples include fully differential input signals, where in + and in C are driven 180 degrees out-of-phase with respect to each other centered around a common mode voltage (v in +? +? v in C )/2, and pseudo-differential true bipolar input signals, where in + swings above and below a ground reference level, driven on in C . regardless of the chosen softspan range, the wide common mode input range and high cmrr of the in + /in C analog inputs allow them to swing with an arbitrary relationship to each other, provided each pin remains between (v cc C 4v) and (v ee ?+? 4v). the output data format for all bipolar softspan ranges is twos complement. unipolar softspan input ranges for channels configured in softspan ranges 5, 4, or 1, the LTC2358-16 digitizes the differential analog input voltage (v in + C v in C) over a unipolar span of 0v to 2.5? ??v refbuf , 0v to 2.5? ??v refbuf /1.024, or 0v to 1.25? ??v refbuf , respec - tively, as shown in table 1a. these softspan ranges are useful for digitizing input signals where in + remains above in C . a traditional example includes pseudo-differential unipolar input signals, where in + swings above a ground reference level, driven on in C . regardless of the chosen softspan range, the wide common mode input range and high cmrr of the in + /in C analog inputs allow them to swing with an arbitrary relationship to each other, provided each pin remains between (v cc C 4v) and (v ee ? +? 4v). the output data format for all unipolar softspan ranges is straight binary. input drive circuits the cmos buffer input stage offers a very high degree of transient isolation from the sampling process. most sen - sors, signal conditioning amplifiers and filter networks with less than 10k of impedance can drive the passive 3pf analog input capacitance directly. for higher impedances and slow-settling circuits, add a 680pf capacitor at the pins to maintain the full dc accuracy of the LTC2358-16. the very high input impedance of the unity gain buffers in the LTC2358-16 greatly reduces the drive requirements of the differential amplifier and make it possible to include optional rc filters with k impedance and arbitrarily slow time constants for anti-aliasing or other purposes. micro- power op amps with limited drive capability are also well suited to drive the high impedance analog inputs directly. the ltc2358 -16 features proprietary circuitry to achieve exceptional internal crosstalk isolation between channels (109db typical). the pc board wiring to the analog inputs should be short and shielded to prevent external capacitive crosstalk between channels. the capacitance between adja - cent package pins is 0.16pf. low source resistance and/or high source capacitance help reduce external capacitively coupled crosstalk. single ended input drive also enjoys additional external crosstalk isolation because every other input pin is grounded, or at a low impedance dc source, and serves as a shield between channels. input overdrive tolerance driving an analog input above v cc on any channel up to 10ma will not affect conversion results on other channels. approx - imately 70% of this overdrive current will flow out of the v cc pin and the remaining 30% will flow out of v ee . this current flowing out of v ee will produce heat across the v cc C v ee voltage drop and must be taken into account for the total absolute maximum power dissipation of 500mw. driving an analog input below v ee may corrupt conversion results on other channels. this product can handle input currents of up to 100ma below v ee or above v cc without latchup. keep in mind that driving the inputs above v cc or below v ee may reverse the normal current flow from the external power supplies driving these pins. lt c2358-16 rev a
22 for more information www.analog.com applications information feature of the LTC2358-16 enables it to accept a wide variety of signal swings, simplifying signal chain design. the two-tone test shown in figure 6b demonstrates the arbitrary input drive capability of the ltc2358 -16. this test simultaneously drives in + with a ? 7dbfs 2khz single-ended sine wave and in ? with a ?7dbfs 3.1khz single-ended sine wave. together, these signals sweep the analog inputs across a wide range of common mode and differential mode voltage combinations, similar to the more general arbitrary input signal case. they also have a simple spec - tral representation. an ideal differential converter with no common-mode sensitivity will digitize this signal as two ?7dbfs spectral tones, one at each sine wave frequency. the fft plot in figure 6b demonstrates the LTC2358-16 response approaches this ideal, with 119db of sfdr limited by the converter's second harmonic distortion response to the 3.1khz sine wave on in C . the ability of the ltc2358 -16 to accept arbitrary signal swings over a wide input common mode range with high cmrr can simplify application solutions. in practice, many sensors produce a differential sensor voltage riding on top of a large common mode signal. figure 7a depicts one way of using the LTC2358-16 to digitize signals of this type. the amplifier stage provides a differential gain of approximately 10v/v to the desired sensor signal while the unwanted common mode signal is attenuated by the adc cmrr. the circuit employs the 5v softspan range of the adc. figure 7b shows measured cmrr performance of this solution, which is competitive with the best com - mercially available instrumentation amplifiers. figure 7c shows measured ac performance of this solution. in figure 8, another application circuit is shown which uses two channels of the LTC2358-16 to simultaneously sense the voltage and bidirectional current through a sense resistor over a wide common mode range. input filtering the true high impedance analog inputs can accommodate a very wide range of passive or active signal conditioning filters. the buffered adc inputs have an analog bandwidth of 6mhz, and impose no particular bandwidth requirement on external filters. the external input filters can therefore be optimized independent of the adc to reduce signal chain noise and interference. a common filter configuration is the simple anti-aliasing and noise reducing rc filter with its pole at half the sampling frequency. for example, 100khz with r=2.43k and c=680pf as shown in figure 5. ?15v 15v LTC2358-16 235816 f05 only channel 0 shown for clarity true bipolar +10v 0v ?10v +10v 0v ?10v unipolar 0.1f 0.1f 0.1f 47f in0 + in0 ? v cc refin refbuf v ee optional lowpass filter 680pf r = 2.43k in + in ? figure 5. filtering single-ended input signals high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo/cog and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. arbitrary and fully differential analog input signals the wide common mode input range and high cmrr of the ltc2358 -16 allow each channel s in + and in C pins to swing with an arbitrary relationship to each other, provided each pin remains between (v cc C 4v) and (v ee ?+? 4v). this lt c2358-16 rev a
23 for more information www.analog.com applications information ?15v 15v LTC2358-16 235816 f06a only channel 0 shown for clarity fully differential +10v 0v ?10v true bipolar +10v 0v ?10v arbitrary +10v 0v ?10v unipolar 0.1f 0.1f 0.1f 47f +5v 0v ?5v in0 + in0 ? v cc refin refbuf v ee in + in ? figure 6a. input arbitrary, fully differential, true bipolar, and unipolar signals figure 6b. two-tone test. in + = C 7dbfs 2khz sine, in C ? = ? C 7dbfs 3.1khz sine, 32k point fft, f smpl = 200ksps. circuit?shown in figure 6a figure 6c. in + /in C = C 1dbfs 2khz fully differential sine, v cm ? = ? 0v, 32k point fft, f smpl = 200ksps . circuit shown in figure 6a figure 6d. in + = C1dbfs 2khz true bipolar sine, in C = 0v, 32k point fft, f smpl = 200ksps. circuit shown in figure 6a figure 6e. in + = C1dbfs 2khz unipolar sine, in C = 0v, 32k point fft, f smpl = 200ksps. circuit shown in figure 6a lt c2358-16 rev a 60 235816 f06e 80 100 ?180 ?160 ?140 ?120 ?100 ?80 ?60 10.24v range ?40 ?20 0 amplitude (dbfs) arbitrary drive 235816 f06b 10.24v range snr = 94.3db thd = ?115db sinad = 94.3db sfdr = 118db sfdr = 120db frequency (khz) 0 20 40 60 80 100 ?180 ?160 snr = 94.3db ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) fully differential drive 6.2khz 235816 f06c 10.24v range snr = 94.3db thd = ?111db sinad = 94.2db sfdr = 113db frequency (khz) 0 20 40 frequency (khz) 60 80 100 ?180 ?160 ?140 ?120 ?100 ?80 ?60 0 ?40 ?20 0 amplitude (dbfs) true bipolar drive 235816 f06d 0v to 10.24v range snr = 89.9db thd = ?114db sinad = 89.8db 20 sfdr = 115db frequency (khz) 0 20 40 60 80 100 ?180 ?160 40 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) unipolar drive
24 for more information www.analog.com ?7v ?7v 31v buffered analog inputs 31v LTC2358-16 235816 f07a only channel 0 shown for clarity 24v 0v arbitrary + ? + ? 0.1f 0.1f 0.1f 47f in0 + in0 ? ltc2057hv ltc2057hv v cc refin refbuf v ee internal hi-z buffers allow optional k passive filters gain = 10 bw = 10khz 2.2nf 3.65k 3.65k 549 in + in ? 2.49k 2.49k common mode input range differential mode input range: 500mv applications information figure 7b. cmrr vs input frequency. circuit shown in figure 7a figure 7c. in + /in C ? = ? 450mv 200hz fully differential sine, 0v??v cm ??24v, 32k point fft, f smpl ?=?200ksps. circuit shown in figure 7a ?15v 15v LTC2358-16 235816 f08 only channels 0 and 1 shown for clarity 0.1f 0.1f 0.1f 47f ?10.24v v s1 10.24v ?10.24v v s2 10.24v v s1 ? v s2 r sense i sense = in0 + in0 ? in1 + in1 ? v cc refin refbuf v ee i sense r sense v s2 v s1 figure 8. simultaneously sense voltage (ch0) and current (ch1) over a wide common mode range figure 7a. amplify differential signals with gain of 10 over a wide common mode range with buffered analog inputs lt c2358-16 rev a 70 80 90 100 110 120 130 140 150 160 5v range cmrr (db) 235816 f07b snr = 90.5db thd = ?111db sinad = 90.4db sfdr = 112db 5v range fully differential drive (in ? = ?in + ) frequency (khz) 0 in + = in ? = 1v p?p sine 20 40 60 80 100 ?180 ?160 ?140 ?120 ?100 frequency (hz) ?80 ?60 ?40 ?20 0 amplitude (dbfs) 235816 f07c 10 100 1k 10k 60
25 for more information www.analog.com adc reference as shown previously in table 1b, the LTC2358-16 supports three reference configurations. the first uses both the in - ternal bandgap reference and reference buffer. the second externally overdrives the internal reference but retains the internal buffer, which isolates the external reference from adc conversion transients. this configuration is ideal for sharing a single precision external reference across multiple adcs. the third disables the internal buffer and overdrives the refbuf pin externally. internal reference with internal buffer the LTC2358-16 has an on-chip, low noise, low drift (20ppm/c maximum), temperature compensated band - gap reference that is factory trimmed to 2.048v. the reference output connects through a 20k resistor to the refin pin, which serves as the input to the on-chip reference buffer, as shown in figure 9a. when employing the internal bandgap reference, the refin pin should be bypassed to gnd (pin 20) close to the pin with a 0.1f ceramic capacitor to filter wideband noise. the reference buffer amplifies v refin to create the converter master reference voltage v refbuf = 2? ??v refin on the refbuf pin, nominally 4.096v when using the internal bandgap refer - ence. bypass refbuf to gnd (pin 20) close to the pin with at least a 47f ceramic capacitor (x7r, 10v, 1210 size or x5r, 10v , 0805 size) to compensate the reference buffer, absorb transient conversion currents, and minimize noise. external reference with internal buffer if more accuracy and/or lower drift is desired, refin can be easily overdriven by an external reference since 20k of resistance separates the internal bandgap reference output from the refin pin, as shown in figure 9b . the valid range of external reference voltage overdrive on the refin pin is 1.25v to 2.2v, resulting in converter master reference voltages v refbuf between 2.5v and 4.4v, re - spectively. analog devices, inc. offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power, and high accuracy, the ltc6655 -2.048 is well suited for use with the LTC2358-16 when overdriving the internal reference. the applications information 235816 f09a 47f 6.5k 20k LTC2358-16 refbuf refin gnd bandgap reference 6.5k 0.1f reference buffer figure 9a. internal reference with internal buffer configuration 235816 f09b 47f 6.5k 20k LTC2358-16 refbuf refin gnd bandgap reference 6.5k 2.7f ltc6655-2.048 reference buffer figure 9b. external reference with internal buffer configuration 235816 f09c 47f 6.5k 20k LTC2358-16 refbuf refin gnd bandgap reference 6.5k ltc6655-5 reference buffer figure 9c. external reference with disabled internal buffer configuration lt c2358-16 rev a
26 for more information www.analog.com lt c6655 -2.048 offers 0.025% (maximum) initial accuracy and 2ppm/c (maximum) temperature coefficient for high precision applications. the ltc6655-2.048 is fully speci - fied over the h-grade temperature range, complementing the extended temperature range of the LTC2358-16 up to 125 c . bypassing the ltc6655-2.048 with a 2.7f to 100f ceramic capacitor close to the refin pin is recommended. external reference with disabled internal buffer the internal reference buffer supports v refbuf = 4.4v maximum. by grounding refin, the internal buffer may be disabled allowing refbuf to be overdriven with an external reference voltage between 2.5v and 5v, as shown in figure 9c. maximum input signal swing and snr are achieved by overdriving refbuf using an external 5v reference. the buffer feedback resistors load the refbuf pin with 13k even when the reference buffer is disabled. the ltc6655 -5 offers the same small size, accuracy, drift, and extended temperature range as the ltc6655-2.048, and achieves a typical snr of 94.8db when paired with the LTC2358-16. bypass the ltc6655-5 to gnd (pin 20) close to the refbuf pin with at least a 47f ceramic ca - pacitor (x7r, 10v, 1210 size or x5r, 10v, 0805 size) to absorb transient conversion currents and minimize noise. the ltc2358 -16 converter draws a charge (q conv ) from the refbuf pin during each conversion cycle. on short time scales most of this charge is supplied by the external refbuf bypass capacitor, but on longer time scales all of the charge is supplied by either the reference buffer, or when the internal reference buffer is disabled, the external reference. this charge draw corresponds to a dc current equivalent of i refbuf = q conv ? ? ?f smpl , which is proportional to sample rate. in applications where a burst of samples is taken after idling for long periods of time, as shown in figure 10, i refbuf quickly transitions from approximately 0.4ma to 1.5ma (v refbuf = 5v, f smpl ? =? 200khz). this current step triggers a transient response in the external reference that must be considered, since any deviation in v refbuf affects converter accuracy. if an external reference is used to overdrive refbuf, the fast settling ltc6655 family of references is recommended. internal reference buffer transient response for optimum performance in applications employing burst sampling, the external reference with internal reference buffer configuration should be used. the internal reference buffer incorporates a proprietary design that minimizes movements in v refbuf when responding to a burst of conversions following an idle period. figure 11 compares the burst conversion response of the LTC2358-16 with an input near full scale for two reference configurations. the first configuration employs the internal reference buffer with refin externally overdriven by an ltc6655-2.048, while the second configuration disables the internal ref - erence buffer and overdrives refbuf with an external ltc6655-4.096. in both cases refbuf is bypassed to gnd with a 47f ceramic capacitor. figure 11. burst conversion response of the LTC2358-16, f smpl? =?200ksps applications information cnv idle period idle period 235816 f10 figure 10. cnv waveform showing burst sampling lt c2358-16 rev a 200 300 400 500 ?5.0 ?2.5 0 2.5 5.0 7.5 internal reference buffer 10.0 deviation from final value (lsb) 235816 f11 external reference on refbuf 10.24v range in + = 10v in ? = 0v time (s) 0 100
27 for more information www.analog.com dynamic performance fast fourier transform (fft) techniques are used to test the adcs frequency response, distortion, and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the LTC2358-16 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies below half the sampling frequency, exclud - ing dc. figure 12 shows that the LTC2358-16 achieves a typical sinad of 94.1db in the 10.24v range at a 200khz sampling rate with a true bipolar 2khz input signal. signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 12 shows that the LTC2358-16 achieves a typical snr of 94.2db in the 10.24v range at a 200khz sampling rate with a true bipolar 2khz input signal. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: t h d = 2 0 l o g v 2 2 + v 3 2 + v 4 2 . . . v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre - quency and v 2 through v n are the amplitudes of the second through nth harmonics, respectively. figure 12 shows that the LTC2358-16 achieves a typical thd of C111db (n? = ?6) in the 10.24v range at a 200khz sampling rate with a true bipolar 2khz input signal. figure 12. 32k point fft f smpl = 200ksps, f in = 2khz power considerations the LTC2358-16 requires four power supplies: the posi - tive and negative high voltage power supplies (v cc and v ee ), the 5v core power supply (v dd ) and the digital input/ output (i/o) interface power supply (ov dd ). as long as the voltage difference limits of 10v v cc C v ee 38v are observed, v cc and v ee may be independently biased anywhere within their own individual allowed operating ranges, including the ability for v ee to be tied directly to ground. this feature enables the common mode input range of the LTC2358-16 to be tailored to the specific applications requirements. the flexible ov dd supply al - lows the LTC2358-16 to communicate with cmos logic operating between 1.8v and 5v, including 2.5v and 3.3v systems. when using lvds i/o mode, the range of ov dd is 2.375v to 5.25v. power supply sequencing the LTC2358-16 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the LTC2358-16 has an internal power-on-reset (por) circuit which resets the applications information lt c2358-16 rev a 40 60 80 100 ?180 ?160 ?140 ?120 ?100 ?80 10.24v range ?60 ?40 ?20 0 amplitude (dbfs) 235816 f12 snr = 94.2db thd = ?111db sinad = 94.1db sfdr = 113db frequency (khz) 0 20
28 for more information www.analog.com converter on initial power-up and whenever v dd drops below 2v. once the supply voltage re-enters the nominal supply voltage range, the por reinitializes the adc. no conversions should be initiated until at least 10ms after a por event to ensure the initialization period has ended. when employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the refbuf bypass capacitor. any conversion initiated before these times will produce invalid results. timing and control cnv timing the LTC2358-16 sampling and conversion is controlled by cnv. a rising edge on cnv transitions all channels s/h circuits from track mode to hold mode, simultaneously sampling the input signals on all channels and initiating a conversion. once a conversion has been started, it cannot be terminated early except by resetting the adc, as discussed in the reset timing section. for optimum performance, drive cnv with a clean, low jitter signal and avoid transitions on data i/o lines leading up to the rising edge of cnv. additionally, to minimize channel-to-channel crosstalk, avoid high slew rates on the analog inputs for 100ns before and after the rising edge of cnv. converter status is indicated by the busy output, which transitions low-to-high at the start of each conversion and stays high until the conversion is complete. once cnv is brought high to begin a conversion, it should be returned low between 40ns and 60ns later or after the falling edge of busy to minimize external disturbances during the internal conver - sion process. the cnv timing required to take advantage of the reduced power nap mode of operation is described in the nap mode section. internal conversion clock the LTC2358-16 has an internal clock that is trimmed to achieve a maximum conversion time of 550?n ns with n channels enabled. with a minimum acquisition time of 570ns when converting eight channels simultaneously, throughput performance of 200ksps is guaranteed without any external adjustments. also note that the minimum acquisition time varies with sampling frequency (f smpl ) and the number of enabled channels. nap mode the LTC2358-16 can be placed into nap mode after a con - version has been completed to reduce power consumption between conversions. in this mode a portion of the device circuitry is turned off, including circuits associated with sampling the analog input signals. nap mode is enabled by keeping cnv high between conversions, as shown in figure 13. to initiate a new conversion after entering nap mode, bring cnv low and hold for at least 750ns before bringing it high again. the converter acquisition time (t acq ) is set by the cnv low time (t cnvl ) when using nap mode. power down mode when pd is brought high, the LTC2358-16 is powered down and subsequent conversion requests are ignored. if this occurs during a conversion, the device powers down once the conversion completes. in this mode, the device applications information cnv t conv t acq busy nap nap mode t cnvl 235816 f13 figure 13. nap mode timing for the LTC2358-16 lt c2358-16 rev a
29 for more information www.analog.com draws only a small regulator standby current resulting in a typical power dissipation of 0.68mw . to exit power down mode, bring the pd pin low and wait at least 10ms before initiating a conversion. when employing the internal refer - ence buffer, allow 200ms for the buffer to power up and recharge the refbuf bypass capacitor. any conversion initiated before these times will produce invalid results. reset timing a global reset of the ltc2358 -16, equivalent to a power- on-reset event, may be executed without needing to cycle the supplies. this feature is useful when recovering from system-level events that require the state of the entire sys - tem to be reset to a known synchronized value. to initiate a global reset, bring pd high twice without an intervening conversion, as shown in figure 14. the reset event is trig - gered on the second rising edge of pd, and asynchronously ends based on an internal timer. reset clears all serial data output registers and restores the internal softspan configu - ration register default state of all channels in softspan?7. if reset is triggered during a conversion, the conversion is immediately halted. the normal power down behavior associated with pd going high is not affected by reset. once pd is brought low, wait at least 10ms before initiating a conversion. when employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the refbuf bypass capacitor. any conversion initiated before these times will produce invalid results. power dissipation vs sampling frequency when nap mode is employed, the power dissipation of the LTC2358-16 decreases as the sampling frequency is applications information reduced, as shown in figure 15. this decrease in aver - age power dissipation occurs because a portion of the ltc2358 -16 circuitry is turned off during nap mode, and the fraction of the conversion cycle (t cyc ) spent napping increases as the sampling frequency (f smpl ) is decreased. figure 15. power dissipation of the LTC2358-16 decreases with decreasing sampling frequency digital interface the ltc2358 -16 features cmos and lvds serial interfaces, selectable using the lvds/ cmos pin. the flexible ov dd supply allows the LTC2358-16 to communicate with any cmos logic operating between 1.8v and 5v, including 2.5v and 3.3v systems, while the lvds interface supports low noise digital designs. in cmos mode, applications may employ between one and eight lanes of serial data output, allowing the user to optimize bus width and data throughput. together, these i/o interface options enable the LTC2358-16 to communicate equally well with legacy microcontrollers and modern fpgas. cnv t conv t cnvh t pdh t pdl busy reset reset time set internally second rising edge of pd triggers reset pd t wake 235816 f14 figure 14. reset timing for the LTC2358-16 lt c2358-16 rev a 40 80 120 160 200 ?6 ?4 ?2 0 2 i ovdd 4 6 8 10 12 14 16 supply current (ma) 235816 f15 i vdd i vee i vcc with nap mode t cnvl = 1s sampling frequency (khz) 0
30 for more information www.analog.com applications information serial cmos i/o mode as shown in figure 16, in cmos i/o mode the serial data bus consists of a serial clock input, scki, serial data input, sdi, serial clock output, scko, and eight lanes of serial data output, sdo0 to sdo7. communication with the LTC2358-16 across this bus occurs during predefined data transaction windows. within a window, the device accepts 24-bit softspan configuration words for the next conversion on sdi and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on sdo0 to sdo7. new data transaction windows open 10ms after powering up or resetting the LTC2358-16, and at the end of each con - version on the falling edge of busy. in the recommended use case, the data transaction should be completed with a minimum t quiet time of 20ns prior to the start of the next conversion, as shown in figure 16. new softspan configuration words are only accepted within this recom - mended data transaction window, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion. it is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended. just prior to the falling edge of busy and the opening of a new data transaction window, scko is forced low and sdo0 to sdo7 are updated with the latest conversion results from analog input channels 0 to 7, respectively. rising edges on scki serially clock conversion results and analog input channel configuration information out on sdo0 to sdo7 and trigger transitions on scko that are skew-matched to the data on sdo0 to sdo7. the resulting scko frequency is half that of scki. scki rising edges also latch softspan configuration words provided on sdi, c2 c1 c0 c2 c1 c0 s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3 s4 s1 s2 s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 ss1 ss2 ss0 d15 cnv cs = pd = 0 don?t care t acq busy sdo7 scko sdo0 scki sdi don?t care sample n recommended data transaction window sample n + 1 softspan configuration word for conversion n + 1 channel 0 24-bit packet conversion n channel 1 24-bit packet conversion n channel 7 24-bit packet conversion n channel 0 24-bit packet conversion n 235816 f16 conversion result channel id softspan conversion result d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 ss1 ss2 ss0 d15 don?t care conversion result channel id softspan conversion result ? ? ? t scki t sckih t busylh t sckil t hsdoscki t dsdoscki t ssdiscki t quiet t hsdiscki t dsdobusyl t cnvh t skew t conv t cnvl t cyc figure 16. serial cmos i/o mode lt c2358-16 rev a
31 for more information www.analog.com which are used to program the internal 24-bit softspan configuration register. see the section programming the softspan configuration register in cmos i/o mode for further details. scki is allowed to idle either high or low in cmos i/o mode. as shown in figure 17, the cmos bus is enabled when cs is low and is disabled and hi-z when cs is high, allowing the bus to be shared across multiple devices. the data on sdo0 to sdo7 are grouped into 24- bit packets consisting of a 16-bit conversion result followed by two zeros, 3-bit analog channel id, and 3- bit softspan code, all presented msb first. as suggested in figures 16 and 17, each sdo lane outputs these packets for all analog input channels in a sequential, circular manner. for example, the first 24-bit packet output on sdo0 corresponds to analog input channel 0, followed by the packets for chan - nels 1 through 7. the data output on sdo0 then wraps back to channel 0, and this pattern repeats indefinitely. other sdo lanes follow a similar circular pattern, except the first packet presented on each lane corresponds to its associated analog input channel. when interfacing the LTC2358-16 with a standard spi bus, capture output data at the receiver on rising edges of scki. scko is not used in this case. multiple sdo lanes are also usually not useful in this case. in other applica - tions, such as interfacing the LTC2358-16 with an fpga or cpld, rising and falling edges of scko may be used to capture serial output data on sdo0 to sdo7 in double data rate (ddr) fashion. capturing data using scko adds robustness to delay variations over temperature and supply. full eight lane serial cmos output data capture as shown in table 2, full 200ksps per channel throughput can be achieved with a 45mhz scki frequency by capturing the first packet (24 scki cycles total) from all eight serial data output lanes sdo0 to sdo7. this configuration also allows conversion results from all channels to be captured using as few as 16 scki cycles if the 3-bit analog channel id and 3- bit softspan code are not needed and the device softspan configuration is not being changed. multi-lane data capture is usually best suited for use with fpga or cpld capture hardware, but may be useful in other application-specific cases. applications information cs pd = 0 don?t care busy sdo7 scko sdo0 scki sdi don?t care don?t care don?t care 235816 f17 hi-z hi-z channel 0 packet channel 1 packet channel 2 packet channel 3 packet (partial) hi-z hi-z hi-z hi-z channel 7 packet channel 0 packet channel 1 packet channel 2 packet (partial) ? ? ? new softspan configuration word (overwrites internal config register) two all-zero words and one partial word (internal config register retains current value) t en t dis figure 17. internal softspan configuration register behavior. serial cmos bus response to cs lt c2358-16 rev a
32 for more information www.analog.com fewer than eight lane serial cmos output data capture applications that cannot accommodate the full eight lanes of serial data capture may employ fewer lanes without reconfiguring the LTC2358-16. for example, capturing the first two packets (48 scki cycles total) from sdo0, sdo2, sdo4, and sdo6 provides data for analog input channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respec - tively, using four output lanes. similarly, capturing the first four packets (96 scki cycles total) from sdo0 and sdo4 provides data for analog input channels 0 to 3 and 4 to 7, respectively, using two output lanes. if only one lane can be accommodated, capturing the first eight packets (192 scki cycles total) from sdo0 provides data for all analog input channels. as shown in table 2, full 200ksps per channel throughput can be achieved with a 90mhz scki frequency in the four lane case, but the maximum cmos scki frequency of 100mhz limits the throughput to less than 200ksps per channel in the two lane and one lane cases. finally, note that in choosing the number of lanes and which lanes to use for data capture, the user is not restricted to the specific cases mentioned above. other choices may be more optimal in particular applications. programming the softspan configuration register in cmos i/o mode the internal 24-bit softspan configuration register con - trols the softspan range for all analog input channels of the LTC2358-16. the default state of this register after power-up or resetting the device is all ones, configuring each channel to convert in softspan 7, the 2.5 ? v refbuf range (see table 1a). the state of this register may be modified by providing a new 24- bit softspan configuration word on sdi during the data transaction window shown in figure 16. new softspan configuration words are only accepted within this recommended data transaction win - dow, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion. setting a channels softspan code to ss[2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in t conv on the next conversion. similarly, enabling a previously disabled chan - nel requires no additional analog input settling time before starting the next conversion. the mapping between the serial softspan configuration word, the internal softspan configuration register, and each channel s 3-bit softspan code is illustrated in figure 18. applications information table 2. required scki frequency to achieve various throughputs in common output bus configurations with eight channels enabled. shaded entries denote throughputs that are not achievable in a given configuration. calculated using f scki = (number of scki cycles)/(t acq(min) ?C?t quiet ) i/o mode number of sdo lanes number of scki cycles required f scki (mhz) to achieve throughput of 200ksps/channel (t acq ?=?570ns) 100ksps/channel (t acq ?=?5570ns) 50ksps/channel (t acq ?=?15570ns) cmos 8 16 30 3 2 8 24 45 5 2 4 48 90 9 4 2 96 not achievable 18 7 1 192 not achievable 35 13 lvds 1 96 180 (360mbps) 18 (36mbps) 7 (14mbps) lt c2358-16 rev a
33 for more information www.analog.com if fewer than 24 scki rising edges are provided during a data transaction window, the partial word received on sdi will be ignored and the softspan configuration register will not be updated. if exactly 24 scki rising edges are provided, the softspan configuration register will be updated to match the received softspan configuration word, s[23:0]. the one exception to this behavior occurs when s[23:0] is all zeros. in this case, the softspan configuration register will not be updated, allowing applications to retain the current softspan configuration state by idling sdi low. if more than 24 scki rising edges are provided during a data transaction window, each complete 24-bit word received on sdi will be interpreted as a new softspan configuration word and applied to the softspan configuration register as described above. any partial words are ignored. typically, applications will update the softspan configura - tion register in the manner shown in figures 16 and 17. after the opening of a new data transaction window at the falling edge of busy, the user supplies a 24-bit softspan configuration word on sdi during the first 24 scki cycles. this new word overwrites the internal configuration register contents following the 24th scki rising edge. the user then holds sdi low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional scki cycles applied. softspan settings may be retained across multiple conversions by holding sdi low for the entire data transaction window, regardless of the number of scki cycles applied. serial lvds i/o mode in lvds i/o mode, information is transmitted using posi - tive and negative signal pairs (lvds + /lvds ? ) with bits differentially encoded as (lvds + ? lvds ? ). these signals are typically routed using differential transmission lines s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3 s4 s1 s2 s0 don?t care scki sdi softspan configuration word cmos i/o mode softspan configuration word internal 24-bit softspan configuration register (same for cmos and lvds ) lvds i/o mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 t scki s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3 s4 s1 s2 s0 don?t care scki (lvds) sdi (lvds) t scki channel 7 softspan code ss[2:0] channel 6 softspan code ss[2:0] channel 5 softspan code ss[2:0] channel 4 softspan code ss[2:0] channel 3 softspan code ss[2:0] channel 2 softspan code ss[2:0] channel 1 softspan code ss[2:0] channel 0 softspan code ss[2:0] 235816 f18 t sckih t sckil t ssdiscki t hsdiscki t sckih t sckil t hsdiscki t hsdiscki t ssdiscki t ssdiscki figure 18. mapping between serial softspan configuration word, internal softspan configuration register, and softspan code for each analog input channel applications information lt c2358-16 rev a
34 for more information www.analog.com with 100 characteristic impedance. logical 1s and 0s are nominally represented by differential +350mv and ? 350mv , respectively. for clarity, all lvds timing diagrams and interface discussions adopt the logical rather than physical convention. as shown in figure 19, in lvds i/o mode the serial data bus consists of a serial clock differential input, scki, serial data differential input, sdi, serial clock differential output, scko, and serial data differential output, sdo. communi - cation with the LTC2358-16 across this bus occurs during predefined data transaction windows. within a window, the device accepts 24-bit softspan configuration words for the next conversion on sdi and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on sdo. new data transaction windows open 10ms after powering up or resetting the LTC2358-16, and at the end of each con - version on the falling edge of busy. in the recommended use case, the data transaction should be completed with a minimum t quiet time of 20ns prior to the start of the next conversion, as shown in figure 19. new softspan configuration words are only accepted within this recom - mended data transaction window, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion. it is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended. just prior to the falling edge of busy and the opening of a new data transaction window, sdo is updated with the latest conversion results from analog input channel 0. both rising and falling edges on scki serially clock conversion results and analog input channel configuration information out on sdo. scki is also echoed on scko, skew-matched figure 19. serial lvds i/o mode applications information s23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 24 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s3 s4 s1 s2 s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 ss1 ss2 ss0 d15 d14 d13 cnv (cmos) cs = pd = 0 235816 f19 don?t care t acq busy (cmos) scko (lvds) sdo (lvds) scki (lvds) sdi (lvds) don?t care sample n t cnvl t cyc recommended data transaction window sample n + 1 softspan configuration word for conversion n + 1 channel 0 24-bit packet conversion n channel 1 24-bit packet conversion n channel 7 24-bit packet conversion n conversion result channel id softspan 186 185 187 188 189 190 191 192 0 ss1 ss2 ss0 d15 channel 0 24-bit packet conversion n conversion result channel id softspan t skew t cnvh t sckih t sckil t busylh t dsdoscki t hsdoscki t dsdobusyl t ssdiscki t ssdiscki t hsdiscki t hsdiscki t quiet t scki t conv c2 c1 c0 c2 c1 c0 lt c2358-16 rev a
35 for more information www.analog.com figure 20. internal softspan configuration register behavior. serial lvds bus response to cs to the data on sdo. whenever possible, it is recommended that rising and falling edges of scko be used to capture ddr serial output data on sdo, as this will yield the best robustness to delay variations over supply and tempera - ture. scki rising and falling edges also latch softspan configuration words provided on sdi, which are used to program the internal 24- bit softspan configuration register. see the section programming the softspan configuration register in lvds i/o mode for further details. as shown in figure 20, the lvds bus is enabled when cs is low and is disabled and hi-z when cs is high, allowing the bus to be shared across multiple devices. due to the high speeds involved in lvds signaling, lvds bus sharing must be carefully considered. transmission line limitations imposed by the shared bus may limit the maximum achievable bus clock speed. lvds inputs are internally terminated with a 100 differential resistor when cs is low, while outputs must be differentially terminated with a 100 resistor at the receiver (fpga). scki must idle in the low state in lvds i/o mode, including when transitioning cs. the data on sdo are grouped into 24- bit packets consisting of a 16- bit conversion result followed by two zeros, 3-bit analog channel id, and 3- bit softspan code, all presented msb first. as suggested in figures 19 and 20, sdo outputs these packets for all analog input channels in a sequential, circular manner. for example, the first 24- bit packet output on sdo corresponds to analog input channel 0, followed by the packets for channels 1 through 7. the data output on sdo then wraps back to channel 0, and this pattern repeats indefinitely. applications information cs (cmos) pd = 0 don?t care busy (cmos) scko (lvds) sdo (lvds) scki (lvds) sdi (lvds) don?t care don?t care don?t care 235816 f20 hi-z hi-z channel 0 packet channel 1 packet channel 2 packet channel 3 packet (partial) hi-z hi-z new softspan configuration word (overwrites internal config register) two all-zero words and one partial word (internal config register retains current value) t en t dis lt c2358-16 rev a
36 for more information www.analog.com serial lvds output data capture as shown in table 2, full 200ksps per channel throughput can be achieved with a 180mhz scki frequency by captur - ing eight packets (96 scki cycles total) of ddr data from sdo. the ltc2358 -16 supports lvds scki frequencies up to 250mhz. programming the softspan configuration register in lvds i/o mode the internal 24-bit softspan configuration register con - trols the softspan range for all analog input channels of the LTC2358-16. the default state of this register after power-up or resetting the device is all ones, configuring each channel to convert in softspan 7, the 2.5 ? v refbuf range (see table 1a). the state of this register may be modified by providing a new 24- bit softspan configuration word on sdi during the data transaction window shown in figure 19. new softspan configuration words are only accepted within this recommended data transaction win - dow, but softspan changes take effect immediately with no additional analog input settling time required before starting the next conversion. setting a channels softspan code to ss[2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in t conv on the next conversion. similarly, enabling a previously disabled chan - nel requires no additional analog input settling time before starting the next conversion. the mapping between the serial softspan configuration word, the internal softspan configuration register, and each channel s 3-bit softspan code is illustrated in figure 18. if fewer than 24 scki edges (rising plus falling) are provided during a data transaction window, the partial word received on sdi will be ignored and the softspan configuration register will not be updated. if exactly 24 scki edges are provided, the softspan configuration register will be updated to match the received softspan configuration word, s[23:0]. the one exception to this behavior occurs when s[23:0] is all zeros. in this case, the softspan configuration register will not be updated, allowing applications to retain the current softspan con - figuration state by idling sdi low. if more than 24 scki edges are provided during a data transaction window, each complete 24-bit word received on sdi will be interpreted as a new softspan configuration word and applied to the softspan configuration register as described above. any partial words are ignored. typically, applications will update the softspan configura - tion register in the manner shown in figures 19 and 20. after the opening of a new data transaction window at the falling edge of busy, the user supplies a 24-bit ddr softspan configuration word on sdi during the first 12 scki cycles. this new word overwrites the internal con - figuration register contents following the 12 th scki falling edge. the user then holds sdi low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional scki cycles applied. softspan settings may be retained across multiple conversions by holding sdi low for the entire data transaction window, regardless of the number of scki cycles applied applications information lt c2358-16 rev a
37 for more information www.analog.com to obtain the best performance from the LTC2358-16, a four-layer printed circuit board (pcb) is recommended. layout for the pcb should ensure the digital and analog signal lines are separated as much as possible. in particu - lar, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. also minimize the length of the refbuf to gnd (pin 20) bypass capacitor return loop, and avoid routing cnv near signals which could potentially disturb its rising edge. supply bypass capacitors should be placed as close as possible to the supply pins. low impedance common re - turns for these bypass capacitors are essential to the low noise operation of the adc. a single solid ground plane is recommended for this purpose. when possible, screen the analog input traces using ground. reference design for a detailed look at the reference design for this con - verter, including schematics and pcb layout, please refer to dc2365, the evaluation kit for the LTC2358-16. board layout lt c2358-16 rev a
38 for more information www.analog.com package description please refer to http: //www.linear.com/product/LTC2358-16#packaging for the most recent package drawings. lx48 lqfp 0113 rev a 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 9.00 bsc a a 7.00 bsc 1 2 7.00 bsc 9.00 bsc 48 1.60 max 1.35 ? 1.45 0.05 ? 0.15 0.09 ? 0.20 0.50 bsc 0.17 ? 0.27 gauge plane 0.25 note: 1. package dimensions conform to jedec #ms-026 package outline 2. dimensions are in millimeters 3. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 4. pin-1 indentifier is a molded indentation, 0.50mm diameter 5. drawing is not to scale see note: 4 c0.30 ? 0.50 r0.08 ? 0.20 7.15 ? 7.25 5.50 ref 1 2 5.50 ref 7.15 ? 7.25 48 package outline recommended solder pad layout apply solder mask to areas that are not soldered section a ? a 0.50 bsc 0.20 ? 0.30 1.30 min lx package 48-lead plastic lqfp (7mm 7mm) (reference ltc dwg # 05-08-1760 rev a) e3 ltcxxxx lx-es q_ _ _ _ _ _ xxyy tray pin 1 bevel package in tray loading orientation component pin ?a1? lt c2358-16 rev a
39 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 05/18 updated max limits for analog input leakage 1, 3 lt c2358-16 rev a
40 for more information www.analog.com www.analog.com ? analog devices, inc. 2016-2018 d16870-0-5/18(a) related parts typical application part number description comments adcs ltc2358-18 18-bit, 200ksps/ch, buffered 8-channel simultaneous sampling, 3.5lsb inl, serial adc 10.24v buffered softspan inputs with 30v p-p common mode range, 96.4db snr, serial cmos and lvds i/o, 7mm 7mm lqfp-48 package ltc2348-18/ltc2348-16 18-/16-bit, 200ksps/ch, 8-channel simultaneous sampling, 3lsb/1lsb inl, serial adc 10.24v softspan inputs with wide common mode range, 97db/94db snr, serial cmos and lvds i/o, 7mm 7mm lqfp-48 package ltc2335-18/ltc2335-16 18-/16-bit, 1msps, 8-channel multiplexed, 3lsb/1lsb inl, serial adc 10.24v softspan inputs with wide common mode range, 97db/94db snr, serial cmos and lvds i/o, 7mm 7mm lqfp-48 package ltc2345-18/ltc2345-16 18-/16-bit, 200ksps/ch, 8-channel simultaneous sampling, 5lsb/1.25lsb inl, serial adc 4.096v softspan inputs with wide common mode range, 92db/91db snr, serial cmos and lvds i/o, 7mm 7mm qfn-48 package ltc2378-20/ltc2377-20/ ltc2376-20 20-bit, 1msps/500ksps/250ksps, 0.5ppm inl serial, low power adc 2.5v supply, 5v fully differential input, 104db snr, msop-16 and 4mm 3mm dfn-16 packages ltc2338-18/ltc2337-18/ ltc2336-18 18-bit, 1msps/500ksps/250ksps, serial, low power adc 5v supply, 10.24v fully differential input, 100db snr, msop-16 package ltc2328-18/ltc2327-18/ ltc2326-18 18-bit, 1msps/500ksps/250ksps, serial, low power adc 5v supply, 10.24v pseudo-differential input, 95db snr, msop-16 package ltc2373-18/ltc2372-18 18-bit, 1msps/500ksps, 8-channel, serial adc 5v supply, 8 channel multiplexed, configurable input range, 100db snr, dgc, 5mm 5mm qfn-32 package ltc2379-18/ltc2378-18/ ltc2377-18/ltc2376-18 18-bit,1.6msps/1msps/500ksps/250ksps, serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps, serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2387-18/ltc2387-16 18-/16-bit, 15msps sar adc 5v supply, differential input, 93.8db snr, 5mm 5mm qfn package ltc1859/ltc1858/ ltc1857 16-/14-/12-bit, 8-channel, 100ksps, serial adc 10v, softspan, single-ended or differential inputs, single 5v supply, ssop-28 package dacs ltc2756/ltc2757 18-bit, serial/parallel i out softspan dac 1lsb inl/dnl, software-selectable ranges, ssop-28/7mm 7mm lqfp-48 package ltc2668 16-channel 16-/ 12-bit 10v v out softspan dacs 4lsb inl, precision reference 10ppm/ c max, 6mm 6mm qfn-40 package references ltc6655 precision low drift low noise buffered reference 5v/ 2.5v/ 2.048v/ 1.25v, 2ppm/ c, 0.25ppm peak-to-peak noise, msop-8 package lt6657 precision low drift low noise buffered reference 5v/ 3v/ 2.5v, 1.5ppm/ c, 0.5ppm peak-to-peak noise, msop-8 package amplifiers ltc2057/ltc2057hv high voltage, low noise zero-drift op amp maximum input offset: 4.5v , supply voltage range: 4.75v to 60v lt6020 dual, micropower, 5v/s, rail-to-rail op amp maximum input offset: 30v, maximum supply current: 100a/amplifier lt1354/lt1355/lt1356 single/dual/quad 1ma, 12mhz, 400v/s op amp good dc precision, stable with all capacitive loads amplify differential signals with gain of 10 over a wide common mode range with buffered analog inputs ?7v ?7v 31v buffered analog inputs 31v LTC2358-16 235816 ta02 only channel 0 shown for clarity 24v 0v arbitrary + ? + ? 0.1f 0.1f 0.1f 47f in0 + in0 ? ltc2057hv ltc2057hv v cc refin refbuf v ee internal hi-z buffers allow optional k passive filters gain = 10 bw = 10khz 2.2nf 3.65k 3.65k 549 in + in ? 2.49k 2.49k common mode input range differential mode input range: 500mv lt c2358-16 rev a

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